ONNC for AI system-on-chips

At least one hundred deep learning accelerators (DLAs) are available in 2018. However, mainstream AI frameworks such as TensorFlow and Caffe are designed only for CPUs and GPUs. In other words, most DLA vendors lack functional support for their designed ASICs. DLA vendors need to reinvent the wheels by implanting AI framework every time they design a new ASICs. This tedious and error-prone process will delay the product launch.

Lacking of performance cost model in current AI frameworks causes these problems. Performance model describes various physical features including memory size, configuration of bus systems, clock cycle of tensor operators, and so on. In short, every DLA chip has its unique cost model that compilers can use for optimizing programs with every identical, abstract algorithm.

Skymizer provides a new generation of compiler to describe variant of performance cost models. Our compiler is based on Open Neural Network Exchange Format (ONNX). It is designed by use-define chain which provides you insights in analyzing the liveness range of each tensor. Our compiler also provides rich analysis passes to help DLA vendors customize their own performance cost models. You can simply modify the cost model and port to different kinds of DLA. Our compiler helps you achieve high performance in a shortened development time.

Skymizer provides you compiler consultants to enhance your deep learning accelerator. Our mission is to continuously improve and deliver high-quality compiler and VM to hardware and software companies.