Implementing a compiler from scratch is not easy. Our package contains off-the-shelf parsers, lowering procedures, and optimization algorithms that can keep you from reinventing the wheel. You merely focus on the core algorithms of your compiler that truly distinguishs your product, and integrate ONNC compiler as the rest. ONNC compiler is designed modularly with well-defined interfaces for ease of integration. Especially ONNC compiler supports integration with TVM and LLVM.
Compiler flow commonly separates into three parts in order: frontend, middleend, and backend. For a DLA compiler, the frontend is expected to support a rich set of model formats, and then make the parsed graph compact and explicit enough for ease of further optimization.
The middleend is expected to partition a model graph into groups, each of which will be lowered into DLA, DSP, or CPU backend, that when working together, can achieve high performance in a heterogeneous system.
The backend is expected to perform hardware-dependent optimization of scheduling and resource allocation to maximize performance and minimize memory footprint.
We abstracted the hardware architecture into a set of pre-defined configurations, like memory size, bus address alignment, functions involved in the pipeline, and so on. We formalized those configurations into an easy-to-learn, so-called machine description language. Then we developed corresponding hardware-dependent algorithms. This way you can easily take advantage of the off-the-shelf hardware-dependent optimizations from ONNC compiler.